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Items
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Specifications
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CPU
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Original Renesas SuperH architecture
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Object code level with SH-1, SH-2 and SH-3 Series
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32-bit internal data bus
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General-register files
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Sixteen 32-bit general registers (eight 32-bit shadow registers)
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Eight 32-bit control registers
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Four 32-bit system registers
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RISC-type instruction set
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Instruction length: 16-bit fixed length for improved code efficiency
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Load-store architecture
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Delayed branch instructions
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Instruction set based on C language
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Instruction execution time: one instruction/cycle for basic instructions
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Logical address space: 4 Gbytes
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Space identifier ASID: 8 bits, 256 logical address space
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Five-stage pipeline
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Interrupt controller (INTC)
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23 external interrupt pins (NMI, IRQ5-IRQ0, PINT15 to PINT0)
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On-chip peripheral interrupts: set priority levels for each module
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User break controller (UBC)
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2 break channels
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Addresses, data values, type of access, and data size can all be set as break
conditions
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Supports a sequential break function
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Bus state controller (BSC)
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Physical address space divided into six areas (area 0, areas 2 to 6), each a
maximum of 64 Mbytes, with the following features settable for each area:
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Bus size (8, 16, or 32 bits)
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Number of wait cycles (also supports a hardware wait function)
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Setting the type of space enables direct connection to SRAM, Synchronous DRAM,
and burst ROM
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Supports PCMCIA interface (2 channels)
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Outputs chip select signal (CS0, CS2-CS6) for corresponding area
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Synchronous DRAM refresh function
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Programmable refresh interval
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Support self-refresh mode
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Synchronous DRAM burst access function
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Usable as either big or little endian machine
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Direct memory access controller (DMAC)
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4 channels
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Burst mode and cycle-steal mode
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Data transfer size: 8-/16-/32-bit and 16-byte
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I/O Ports
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A/D converter
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10 bits ± 4 LSB, 4channels
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Conversion time: 16 μs
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Input range: 0-AVcc (max. 3.6 V)
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D/A converter
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8 bits ± 4 LSB, 2 channels
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Conversion time: 10 μs
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Input range: 0-AVcc (max. 3.6 V)
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Renesas user-debugging Interface (H-UDI)
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E10A emulator support
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JTAG-compliant
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Realtime branch address trace
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1-kB on-chip RAM for fast emulation program execution
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Timer (TMU)
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3-channel auto-reload-type 32-bit timer
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Input capture function
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6 types of counter input clocks can be selected
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32 bit counter's highest operating frequency: 2MHz
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Realtime clock(RTC)
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Built-in clock, calendar functions, and alarm functions
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On-chip 32-kHz crystal oscillator circuit with a maximum resolution (interrupt
cycle) of 1/256 second
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Serial communi-cation interface (SCI)
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Asynchronous mode or clock synchronous mode can be selected
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Full-duplex communication
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Supports smart card interface
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Serial Communication Interface with FIFO
(SCIF0)
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16-byte FIFO for transmission/reception
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DMA can be transferred
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Hardware flow control
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Clock pulse generator (CPG)
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Clock mode: An input clock can be selected from the external input (EXTAL or
CKIO) or crystal oscillator.
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Three types of clocks generated:
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CPU clock: 1-24 times the input clock, maximum 200 MHz
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Bus clock: 1-4 times the input clock, maximum 66.67 MHz
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Peripheral clock: 1/4-4 times the input clock, maximum 33.34 MHz
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Power-down modes:
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Sleep mode
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Standby mode
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Module standby mode
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One-channel watchdog timer
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Memory management unit (MMU)
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4Gbytes of address space, 256 address spaces (ASID 8 bits)
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Supports multiple page sizes: 1, 4 kbytes
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128-entry, 4-way set associative TLB
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Supports software selection of replacement method and random-replacement
algorithms
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Contents of TLB can directly be accessed according to the address mapping
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Cache memory
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16-kbyte cache, mixed instruction/data
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256 entries, 4-way set associative, 16-byte block length
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Write-back, write-through, LRU replacement algorithm
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1-stage write-back buffer
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Maximum 2 ways of the cache can be locked
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Russia (Россия)
